Senior Design Verification Engineer Network Protocols |6 8 yrs

Design Verification (Sr. Verification Engineer)br>br>Position Type Permanentbr>br>Total Experience 6 8 yearsbr>br>Job Location Ahmedabad (C.G.Road) Bangalore (WhiteField), br>br>Candidates for now will work from home until the Pandemic.br>br>Notice Period OPEN Max upto +0 daysbr>br>JOB REQUIREMENTS br>br> Minimum 6 years experience in ASICFPGA verification, including verification of complex ASICs atchiplevelbr>br> Expertise in System Verilog and UVMbr>br> Knowledge of C andor Python preferredbr>br> Networking protocol (i.e. Ethernet, OTN) andor FEC experience is a mustbr>br> Basic knowledge of SerDes and ADCDAC a plusbr>br> Expertise in independently building SVUVM test benchesbr>br> Expertise in developing test cases and test plansbr>br> Functional coverage, code coverage closure experience a mustbr>br> Gate sims and debugging.br>br> Experience in lab validation and bring up activities is a plus