Job Description
SPECTRAFORCE
Data Platform Engineer
SPECTRAFORCE • Los Angeles, CA, United States • via LinkedIn
24 hours ago
Contractor
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Apply on Talent.com
Job highlights
Identified by Google from the original job post
Qualifications
🛠️ Required Skills
Strong experience with:
Snowflake (architecture, administration, performance tuning)
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Benefits
Fully remote with a collaborative, forward-thinking team
Responsibilities
This is a hands-on leadership role responsible for managing the full data engineering ecosystem, enabling scalable analytics, and ensuring alignment with enterprise standards
You will act as the bridge between Data Engineering, Cloud Infrastructure, DevOps, and Security teams, owning the platform and guiding best practices across the organization
🏗️ Platform Ownership & Strategy
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Job description
📢 Job Title: Senior Data Engineer (Data Platform Lead)
📍 Location: Remote (U.S. – Must work PST hours)
📅 Duration: 12-Month Contract
🚀 About the Role
We are seeking a Senior Data Engineer / Data Platform Lead to drive the design, operation, and evolution of a modern enterprise data platform. This is a hands-on leadership role responsible for managing the full data engineering ecosystem, en...
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K2 Space
Principal ASIC Package Design Engineer
K2 Space • Los Angeles, CA, United States • via ZipRecruiter
11 hours ago
$2L–$2.8L a year
Full–time
Apply directly on ZipRecruiter
Job highlights
Identified by Google from the original job post
Qualifications
Bachelor's degree in Packaging Engineering, Mechanical Engineering, Electrical Engineering, or a related field
10+ years of experience in ASIC package design, with deep expertise in FC-BGA
Proven experience delivering high-pin-count, high-performance ASIC packages into production
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Benefits
Base salary range for this role is $200,000 – $280,000 + equity in the company
Salary will be based on several factors including, but not limited to: knowledge and skills, education, and experience level
Comprehensive benefits package including paid time off, medical/dental/vision/ coverage, life insurance, paid parental leave, and many other perks
Responsibilities
We are seeking a Principal ASIC Package Design Engineer to lead advanced ASIC package architecture and execution, with a strong focus on flip-chip BGA (FC-BGA) and multi-chip module (MCM) solutions
This role owns the end-to-end package strategy for high-performance mixed-signal and digital SoCs from early architecture and trade studies through vendor engagement, qualification, and production ramp
You will operate as the technical authority for package design, defining standards, influencing silicon and system architecture, and ensuring first-pass success for complex, high-speed, power-dense ASICs
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Job description
K2 is building the largest and highest-power satellites ever flown, unlocking performance levels previously out of reach across every orbit. Backed by $450M from leading investors including Altimeter Capital, Redpoint Ventures, T. Rowe Price, Lightspeed Venture Partners, Alpine Space Ventures, and others – with an additional $500M in signed contracts across commercial and US government customers – we're mass-producing the highest-power satellite platforms ever built for missions from LEO to deep space.
The rise of heavy-lift launch vehicles is shifting the industry from an era of mass constraint to one of mass abundance, and we believe this new era demands a fundamentally different class of spacecraft. Engineered to survive the harshest radiation environments and to fully capitalize on today's and tomorrow's massive rockets, K2 satellites deliver unmatched capability at constellation scale and across multiple orbits.
With multiple launches planned through 2026 and 2027, we're Building Bigger to develop the solar system and become a Kardashev Type II (K2) civilization. If you are a motivated individual who thrives in a fast-paced environment and you're excited about contributing to the success of a groundbreaking Series C space startup, we'd love for you to apply.
The Role
We are seeking a Principal ASIC Package Design Engineer to lead advanced ASIC package architecture and execution, with a strong focus on flip-chip BGA (FC-BGA) and multi-chip module (MCM) solutions. This role owns the end-to-end package strategy for high-performance mixed-signal and digital SoCs from early architecture and trade studies through vendor engagement, qualification, and production ramp. You will operate as the technical authority for package design, defining standards, influencing silicon and system architecture, and ensuring first-pass success for complex, high-speed, power-dense ASICs.
Responsibilities
• Own ASIC package architecture for FC-BGA and MCM solutions, including substrate stack-up, ball-map strategy, power delivery, signal breakout, and mechanical constraints.
• Lead package-level trade studies across cost, performance, power integrity (PI), signal integrity (SI), thermal, manufacturability, and reliability.
• Define long-term packaging roadmap aligned with future ASIC nodes, bandwidth scaling, and multi-die integration.
• Establish organizational package design standards, methodologies, and best practices.
• Drive detailed design of FC-BGA packages for high-pin-count ASICs with high-speed SerDes, dense power grids, and RF signal content.
• Define and review substrate stack-ups, via strategies, impedance control, escape routing, and reference plane planning.
• Partner with silicon, RF, and systems teams to co-optimize die floorplans and package interfaces.
• Own package-level SI/PI strategy, including high-speed digital interfaces (e.g., SerDes, JESD, Interlaken), power delivery network (PDN) design, and decoupling strategy
• Lead thermal architecture at the package level, including lid selection, TIMs, heat-spreaders, and mechanical interfaces to system cooling.
• Serve as the primary technical interface to substrate vendors, assembly houses, and OSATs.
• Drive material selection, substrate technology choices, and assembly process optimization.
Qualifications
• Bachelor's degree in Packaging Engineering, Mechanical Engineering, Electrical Engineering, or a related field.
• 10+ years of experience in ASIC package design, with deep expertise in FC-BGA.
• Proven experience delivering high-pin-count, high-performance ASIC packages into production.
• Strong understanding of substrate technologies and materials, SI/PI fundamentals at the package level, and thermal management for power-dense ASICs.
• Fluent in SI/PI and EM simulation tools such as SIWave, HFSS, and ADS.
• Experience working directly with OSATs and substrate vendors.
• Knowledge of packaging qualification and test methodologies.
