Job Description
Company Description
Spandsons Horizon Engineering revolutionises the AEC industry by integrating sustainability, AI, IoT, and innovative technologies into project management, Virtual Design Construction, and training programs.. Our commitment to innovation and excellence positions us at the forefront of the industry, continuously pushing the boundaries of what is possible.
About the Program:
Our "Semi-Custom RTL - GDS Flow" program at Shiva Nadar University- Noida is an intensive course designed to equip aspiring engineers with comprehensive knowledge and hands-on skills in the end-to-end ASIC physical design process. Spanning from RTL (Register-Transfer Level) to GDSII (Graphic Data System II), participants gain proficiency with industry-standard Synopsys tools and apply advanced design and verification techniques. This is a one-credit, lecture-based program with dedicated project work.
Job Summary:
We are seeking an experienced and passionate Mentor to guide and support participants in our Semi-Custom RTL - GDS Flow Training Program in Noida. As a Mentor, you will play a crucial role in enhancing the learning experience, providing technical guidance on project work, fostering problem-solving skills, and preparing students for successful careers in ASIC design.
Key Responsibilities:
• Technical Guidance & Support: Provide expert guidance on the ASIC Design Flow, RTL design principles, synthesis, physical design (floorplanning, placement, routing), Static Timing Analysis (STA), and physical verification.
• Project Mentorship: Guide learners through the implementation of the full ASIC flow on chosen digital blocks, helping them develop synthesizable RTL, apply proper timing and design constraints (SDC).
• Outcome Assurance: Support learners in achieving project outcomes, including verified RTL code, functional testbench results, synthesis, implementation, verification reports (timing, power, DRC, LVS, STA), and the final tape-out-ready GDSII file.
• Tool Proficiency Coaching: Assist students in gaining hands-on proficiency with Synopsys tools such as Design Compiler, IC Compiler II, PrimeTime, VCS, and Verdi for various stages of the design process.
• Concept Clarification: Clarify complex concepts related to digital logic, Verilog HDL, design constraints (Setup, Hold, Slack), DFT, Clock Tree Synthesis, IR Drop, EM, DRC, LVS, ERC, and Antenna Effects.
• Problem-Solving Facilitation: Foster analytical thinking and problem-solving by guiding students through design challenges and report interpretation.
• Feedback & Evaluation: Provide constructive feedback on project work and help assess understanding of course outcomes.
Required Qualifications:
• Bachelor's or Master's degree in Electronics Engineering, Electrical Engineering, VLSI Design, or a related field.
• 5+ years of industry experience in ASIC physical design, RTL design, or a related semiconductor role.
• Deep understanding and practical experience with the end-to-end RTL to GDSII flow.
• Proficiency with Synopsys EDA tools (e.g., Design Compiler, IC Compiler II, PrimeTime).
• Strong knowledge of Digital Design, Verilog/VHDL, and Basic CMOS logic.
• Excellent communication, interpersonal, and mentoring skills.
• Ability to simplify complex technical concepts for diverse learners.
Preferred Skills (Bonus Points):
• Experience with DFT (Design For Testability) concepts and tools (e.g., DFT Compiler, ATPG).
• Familiarity with ECO Handling (RTL ECO) and Formal Equivalence Checking.
• Prior experience in teaching, training, or formal mentorship roles.
Why Join Our Team as a Mentor?
• Contribute to the development of the next generation of ASIC design engineers.
• Work with a leading academic institution and an innovative ed-tech platform
• Opportunity to share your expertise and shape future talent.
• Be part of a dynamic and supportive learning environment.
